In a typical computer-related apparatus, there is often a flash memory that is based on a NAND technology. A NAND-based flash memory subsystem typically comprises one or more flash memory chips, a memory controller for executing flash translation code (FTL) code in Read-Only Memory (ROM), a Static Read-Access Memory (SRAM) for maintaining the address mapping information, and a host interface for communicating, such as that of a Personal Computer Memory Card International Association (PCMCIA) for example. In operation, a flash memory device is able to issue commands in association with logical sector addresses of and data resident on the flash device. Within the architecture of the device, typically it is the FTL that translates the commands into basic operational commands of read, write, program and/or erase in relation to physical locations, or sector addresses, of the data (i.e., operational commands).
Flash memory is a popular type of non-volatile computer storage chip having a NAND-based architecture. Flash memories are typically found in memory cards, Universal Serial Bus (USB) flash drives, solid-state drives, and similar products, for general storage and transfer of data. NAND flash memory is also often used to store configuration data in numerous digital products. Example applications of flash memory include personal computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, solid state storage, video games, scientific instrumentation, industrial robotics, routers, communication devices, programmable devices, medical electronics, and so on. Flash memory is popular in applications for consumers because of the robustness of the devices (i.e., shock and water resistance versus disc drives) as well as since flash memory offers fast read access times, as Its mechanical shock resistance helps explain its popularity over hard disks in portable devices; consequently, consumers often expect long-term performance from such devices and are often unfamiliar with the flash endurance limits and disturbance issues that may arise.
As used herein the term “NAND-based architecture” is intended to include those architectures and techniques for memory devices, systems and peripherals which are organized into a plurality of blocks where each block comprises a plurality of pages and each page typically defines an individually addressable physical memory location. Further “NAND-based architectures” are also intended to include any memory architecture, including implementations, in which read disturbance(s) or disturbance events resulting from retrieval of data may occur.
Typically, a flash memory drive is used to provide non-volatile storage to computer systems (such as a PC) by connection via a Universal Serial Bus (USB) or other bus. NAND is a common type of flash memory. Flash memory may be electrically erased and reprogrammed. Typically, the NAND-based architecture flash memory is programmed to read/write in pages, where it may be the entirety of the block that is erased when new data is written to the block or before data can be programmed (or written to) a block or memory cell. As a result, fairly large blocks of data are often erased before new data can be written or rewritten to the block, including some possibly invalid data.
However, the reliability of flash data is often affected by a number of factors including: block degradation, bit detection error, limited write/erase cycles and read disturbances. The block degradation can be addressed by bad block management (BBM) algorithms, the limited write/erase cycles can be addressed by wear leveling (WL) algorithms, and bit detection errors can be addressed by an error correction code (ECC). However, heretofore, read disturbances have not been effectively addressed.
Read disturbances, in particular, present situations for flash performances that result in poor reliability, unexpected bit errors, etc. Additionally, errors in the cell being read with each access and may often result in the same for cells adjacent or proximate to the read cell in blocks. Read disturbances may also become more prevalent where: a cell or page nears or exceeds its read disturbance endurance limit; a selected cell is read and another unaddressed cell is affected (e.g., degraded); a selected cell is read and another unaddressed erased cell is programmed; etc. Further, still other examples of failures related to read disturbance may include the loss of data to adjacent pages where there have been too many reads (or READs) or operational commands to proximate pages.
Manufacturers of the devices typically provide for a manufacturer's limit (i.e., flash endurance limit) where the manufacturer essentially guarantees operation of the gate to perform commands provided the associated gate has performed no more than a predetermined set number of command activities. For example a manufacturer of a flash memory may provide a data sheet that describes the minimal and nominal flash endurance limit (i.e., endurance limit) of their product to be a specific number of read/write cycles. The flash endurance limit is typically the measure of the ability of the flash memory product to perform as a function of accumulated nonvolatile data changes it has undergone during operation. Breaches of endurance limit are typically tracked in a flash memory system by a counter that counts the number of operational commands to a particular block (i.e. “block counter”). It will also be appreciated by those familiar with flash memories that a block is typically determined to be erased once the block counter is equal to or exceeds the flash endurance limit as the block may not function correctly thereafter. As a result, often once the flash endurance limit is reached for a block, the pages within that block and the block data are erased and moved to a new location, the counter for the block is reset to zero, and performance is lessened as is capacity of the device.
However, despite the inclusion of flash endurance limits and specification sheets, read disturbance may still cause interruption, errors, and unexpected performance failures to users of such devices. As a result, it is desirable to mitigate the impact of read disturbance to improve the performance and utility of the device and preferably to do so without overhead consequence. Prior efforts such as migrating data from blocks having high error code correction (ECC) count to another block so as to refresh the data, have been attempted, but do not overcome the challenges. Similarly, the use of a block counter also is also insufficient. Both of these approaches add additional overhead and further limit the utility of the system capacity.
Rather what is needed is a method and system to reduce the impact of disturbance without degrading system performance through optimized activities with minimum overhead consequence.
As used herein the terms device, apparatus, system, etc. are intended to be inclusive, interchangeable, and/or synonymous with one another and other similar arrangements and equipment for purposes of the present invention though one will recognize that functionally each may have unique characteristics, functions and/or operations which may be specific to its individual capabilities and/or deployment.